SiI 1161 PanelLink Receiver
Data Sheet
Actual setup and hold times can be derived from the clock period at the operating frequency of interest. Clock
duty cycle must also be taken into account when calculating setup and hold times.
Setup Time to ODCK: TODCK*TDUTY{min} - TCK2OUT{max}
Hold Time from ODCK: TODCK* (1 - TDUTY{max}) + TCK2OUT{min}
Table 8 shows the calculations required for determining setup and hold timings using the clock period TODCK
specific to the clock frequency when OCK_INV=1. The setup and hold times apply to DE, VSYNC, HSYNC and
Data output pins, as long as the appropriate TCK2OUT value is used for the calculation in each case. The table also
shows calculated setup and hold times for commonly used ODCK frequencies.
Table 8. Sample Calculation of Data Output Setup and Hold Times – OCK_INV=1
Frequency
TCK2OUT (data)
Max
Result
Symbol
Parameter
TODCK
25 MHz
40 ns
=40*40% - 1.2 = 14.8ns
TSU
Data Setup Time to ODCK
=TODCK*TDUTY{min)
82.5 MHz
165 MHz
25 MHz
12 ns
6 ns
=1.2
=12*40% - 1.2 = 3.6ns
=6*40% - 1.2 = 1.2ns
=40*40% - 0.0 = 16.0ns
-TCK2OUT{max}
40 ns
Min
THD
Data Hold Time from ODCK
=TODCK* (1 - TDUTY{max})
+ TCK2OUT{min}
82.5 MHz
165 MHz
12 ns
6 ns
=0.0
=12*40% - 0.0 = 4.8ns
=6*40% - 0.0 = 2.4ns
SiI-DS-0096-D
14
SILICONIMAGE [ Silicon image ]
