SiI 1161 PanelLink Receiver
Data Sheet
PD#
VIL
TPDL
QE[23:0], QO[23:0],
DE, CTL[3:1],
VSYNC, HSYNC
Figure 13. Output Signals Disabled Timing from PD# Active
THSC
DE
SCDT
TFSC
DE
SCDT
Figure 14. SCDT Timing from DE Inactive or Active
Internal
ODCK * 2
ODCK
DE
TST
QE[23:0]
QO[23:0]
FIRST EVEN DATA
SECOND EVEN DATA
FIRST ODD DATA
SECOND ODD DATA
Figure 15. Two Pixels per Clock Staggered Output Timing Diagram
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SiI-DS-0096-D