SiI 1160 PanelLink Transmitter
Data Sheet
Reserved Pins
It is preferable to tie indicated pins HIGH through a 2-5KΩ resistor; direct connection to VCC is not
recommended.
Pin Name
RSVD
Pin #
22
Type
In
Description
Reserved. Must be tied HIGH for normal operation.
Reserved. Must be tied HIGH for normal operation.
Reserved. Must be tied HIGH for normal operation.
RSVD
28
In
RSVD
29
In
RSVD
38
--
Reserved. Should be left unconnected (but can be tied to AVCC for existing
SiI 160 designs).
Power and Ground Pins
Pin Name
VCC
Pin #
8,30,56,88
7,31,57,67,79,89
17,66,81,98
36,44
Type
Power
Ground
Power
Power
Ground
Power
Power
Ground
Description
Digital Core VCC, must be set to 3.3V.
Digital Core GND.
GND
IVCC
Input VCC, must be set to 3.3V.
Analog VCC must be set to 3.3V.
Analog GND.
AVCC
AGND
PVCC1
PVCC2
PGND1
33,37,41,47
18
Primary PLL Analog VCC must be set to 3.3V.
Filter PLL Analog VCC must be set to 3.3V.
85
19
PLL Analog GND. PGND1 should not be directly
connected to PGND2 before being connected to the
GROUND plane. They should be connected individually
to the GROUND plane.
PGND2
86
Ground
PLL Analog GND. PGND2 should not be directly
connected to PGND1 before being connected to the
GROUND plane. They should be connected individually
to the GROUND plane.
SiI-DS-0126-B
10
SILICONIMAGE [ Silicon image ]
