SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.7.44 IDE1 Task File Register 1 – Command Buffering
Address Offset: D4H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IDE1 Task File Command + Status
IDE1 Task File Device+Head
IDE1 Task File Cylinder High
IDE1 Task File Cylinder Low
This register defines one of the IDE Channel #1 Task File registers used for Command Buffered accesses in the SiI 0680A.
The register bits are defined below.
•
Bit [31:24]: IDE1 Task File Command (W). This write-only bit field defines the IDE1 Task File Command
register.
•
•
Bit [31:24]: IDE1 Task File Status (R). This read-only bit field defines the IDE1 Task File Status register.
Bit [23:16]: IDE1 Task File Device+Head (R/W). This bit field defines the IDE1 Task File Device and Head
register.
•
•
Bit [15:08]: IDE1 Task File Cylinder High (R/W). This bit field defines the IDE1 Task File Cylinder High register.
Bit [07:00]: IDE1 Task File Cylinder Low (R/W). This bit field defines the IDE1 Task File Cylinder Low register.
9.7.45 Rserved Register
Address Offset: D8H
Access Type: Read Only
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
•
This bit field is reserved and returns an indeterminate value on a read.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
97
SILICONIMAGE [ Silicon image ]
