SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.7.38 Data Transfer Mode – IDE0
Address Offset: B4H
Access Type: Read/Write
Reset Value: 0x0000_0022
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
This register defines the transfer mode register for IDE Channel #0 in the SiI 0680A. The register bits are defined below.
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Bit [31:08]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [07:06]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [05:04]: Device 1 Transfer Mode (R/W) – IDE0 Device 1 Data Transfer Mode. This bit field is used to set the
data transfer mode on IDE side during PCI DMA transfer: 00B = PIO transfer with IORDY not monitored; 01B =
PIO transfer with IORDY monitored; 10B = normal DMA; and, 11B = Ultra DMA.
When this bit field is set to value other than 00B, SiI 0680A will monitor IORDY for normal PIO transfer.
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Bit [03:02]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [01:00]: Device 0 Transfer Mode (R/W) – IDE0 Device 0 Data Transfer Mode. This bit field is used to set the
data transfer mode on IDE side during PCI DMA transfer: 00B = PIO transfer with IORDY not monitored; 01B =
PIO transfer with IORDY monitored; 10B = normal DMA; and, 11B = Ultra DMA.
When this bit field is set to value other than 00B, SiI 0680A will monitor IORDY for normal PIO transfer.
9.7.39 IDE1 Task File Register 0
Address Offset: C0H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IDE1 Task File Starting Sector
Number
IDE1 Task File Sector Count
IDE1 Task File Features (W)
IDE1 Task File Error (R)
IDE1 Task File Data
This register defines one of the IDE Channel #1 Task File registers in the SiI 0680A. Access to the individual bytes of this
register is determined by the PCI bus Byte Enables at the time of the read or write operation. The register bits are defined
below.
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Bit [31:00]: IDE1 Task File Data (R/W). This bit field defines the IDE1 Task File Data register. This register can
be accessed as an 8-bit, 16-bit, or 32-bit word, depending upon the PCI bus Byte Enables. The data written to
this register must be zero-aligned. To access 8-bit Task File Data, the PCI bus Byte Enable for byte 0 must be
active. To access 16-bit Task File Data, the Byte Enables for byte 1 and byte 0 must be active. To access 32-bit
Task File Data, the Byte Enables for all four bytes must be active.
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Bit [31:24]: IDE1 Task File Starting Sector Number (R/W). This bit field defines the IDE1 Task File Starting
Sector Number register. Access to this bit field is permitted if the PCI bus Byte Enable is active for this byte only.
Bit [23:16]: IDE1 Task File Sector Count (R/W). This bit field defines the IDE1 Task File Sector Count register.
Access to this bit field is permitted if the PCI bus Byte Enable is active for this byte only.
Bit [15:08]: IDE1 Task File Features (W). This write-only bit field defines the IDE1 Task File Features register.
Access to this bit field is permitted if the PCI bus Byte Enable is active for this byte only.
Bit [15:08]: IDE1 Task File Error (R). This read-only bit field defines the IDE1 Task File Error register. Access
to this bit field is permitted if the PCI bus Byte Enable is active for this byte only.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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