SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.7.46 IDE1 Virtual DMA/PIO Read Ahead Byte Count
Address Offset: DCH
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IDE1 Virtual DMA/PIO Read Ahead Byte Count
This register defines the read ahead byte count register for Virtual DMA and PIO Read Ahead transfers on IDE Channel #1 in
the SiI 0680A. In Virtual DMA mode (PCI bus master DMA with PIO transfers on the IDE), all 32 bits are used as the word-
aligned byte count. In PIO Read Ahead mode, only the lower 16 bits are used as the word-aligned byte count. The higher 16
bits must be programmed 0x0000.
9.7.47 IDE1 Task File Timing + Configuration + Status
Address Offset: E0H
Access Type: Read/Write
Reset Value: 0x6515_0100
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Addr Setup
Count
Active Count
Recovery Count
Reserved
This register defines the task file timing register for IDE Channel #1 in the SiI 0680A. See chapter 11 for details on
programming this timing register. The register bits are defined below.
•
•
•
Bit [31:28]: Addr Setup Count (R/W) – IDE1 Address Setup Time Count. This bit field is used for programming
the address setup time relative to IDE1_DIOR_N and IDE1_DIOW_N.
Bit [27:22]: Active Count (R/W) – IDE1 DIOR_N and DIOW_N Active Time Count. This bit field is used for
programming the active time of IDE1_DIOR_N and IDE1_DIOW_N.
Bit [21:16]: Recovery Count (R/W) – IDE1 DIOR_N and DIOW_N Recovery Time Count. This bit field is used
for programming the recovery time of IDE1_DIOR_N and IDE1_DIOW_N.
•
•
Bit [15]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [14] : Watchdog Int Ena ( R/W ) – IDE1 Watchdog Interrupt Enable. This bit is set to enable Interrupt when
Watchdog timer expired.
•
•
Bit [13]: Watchdog Ena (R/W) – IDE1 Watchdog Timer Enable. This bit is set to enable the watchdog timer for
IDE1. This bit is cleared to disable the watchdog timer.
Bit [12]: Watchdog Timeout (R) – IDE1 Watchdog Timer Timeout. This bit set indicates that the watchdog timer
for IDE1 timed out. When enabled, and IORDY monitoring bit is also enabled, during IDE0 PIO opeartion, the
watchdog counter starts counting when IORDY signal is deasserted. If after 256 PCI clocks cycles, the IORDY
signal is still deasserted, the Watchdog Timer is expires, and this bit is set and the SiI 0680A continue its
operation and stop monitoring IORDY signal. Software writes one to clear this bit. Once this bit is cleared, the SiI
0680A starts monitoring IORDY on channel 1 again.
•
•
•
Bit [11]: Interrupt Status (R) – IDE1 Interrupt Status. This bit set indicates that an interrupt is pending on IDE1.
This bit provides real-time status of the IDE1 interrupt pin.
Bit [10]: Virtual DMA Int (R) – IDE1 Virtual DMA Completion Interrupt. This bit set indicates that the Virtual DMA
data transfer has completed. This bit is cleared when bit[0] PBM enable in PCI Bus Master – IDE1 is cleared .
Bit [09]: IORDY Monitoring (R/W) – IDE1 IORDY Monitoring. When this bit is set, IORDY line is monitored for
Task File accesses on channel 1.
•
•
Bit [08:04]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [03]: Channel Tri-State (R/W) – IDE1 Channel Tri-State. This bit is set to tri-state the IDE Channel #1 bus.
This bit is cleared for normal operations.
•
Bit [02]: Channel Rst (R/W) – IDE1 Channel Reset. When this bit is set, IDE Channel # 1 RST signal is
asserted.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
98
SILICONIMAGE [ Silicon image ]
