SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.7.42 IDE1 Read/Write Ahead Data
Address Offset: CCH
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IDE1 Read Ahead Data
This register defines the read ahead data port for PIO transfers on IDE Channel #1 in the SiI 0680A.
This register can be accessed as an 8-bit, 16-bit, or 32-bit word, depending upon the PCI bus byte enables. The data written to
this register must be zero-aligned.
9.7.43 IDE1 Task File Register 0 – Command Buffering
Address Offset: D0H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
IDE1 Task File Starting Sector
Number
IDE1 Task File Sector Count
IDE1 Task File Features (W)
IDE1 Task File Error (R)
IDE1 Task File Data
This register defines one of the IDE Channel #1 Task File registers used for Command Buffered accesses in the SiI 0680A.
Access to the individual bytes of this register is determined by the PCI bus Byte Enables at the time of the read or write
operation. The register bits are defined below.
•
Bit [31:00]: IDE1 Task File Data (R/W). This bit field defines the IDE1 Task File Data register. This register can
be accessed as an 8-bit, 16-bit, or 32-bit word, depending upon the PCI bus byte enables. The data written to
this register must be zero-aligned. To access 8-bit Task File Data, the PCI bus Byte Enable for byte 0 must be
active. To access 16-bit Task File Data, the Byte Enables for byte 1 and byte 3 must be active. To access 32-bit
Task File Data, the Byte Enables for all four bytes must be active.
•
•
•
•
Bit [31:24]: IDE1 Task File Starting Sector Number (R/W). This bit field defines the IDE1 Task File Starting
Sector Number register. Access to this bit field is permitted only if the PCI bus Byte Enable for byte 3 is active.
Bit [23:16]: IDE1 Task File Sector Count (R/W). This bit field defines the IDE1 Task File Sector Count register.
Access to this bit field is permitted only if the PCI bus Byte Enable for byte 2 is active.
Bit [15:08]: IDE1 Task File Features (W). This write-only bit field defines the IDE1 Task File Features register.
Access to this bit field is permitted only if the PCI bus Byte Enable for byte 1 is active.
Bit [15:08]: IDE1 Task File Error (R). This read-only bit field defines the IDE1 Task File Error register. Access
to this bit field is permitted only if the PCI bus Byte Enable for byte 1 is active.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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