SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.3 Internal Register Space – Base Address 1
These registers are 32-bits wide and define the internal operation of the SiI 0680A. The access types are defined as follows:
R=read, W=write, and C=clearable by some write operation. Access to this register is through the PCI I/O space.
Address
Offset
Register Name
Access
Type
31
16
15
00
00H
Reserved
IDE0 TF Device
Reserved
Reserved
R/W
Control
Auxiliary Status
Table 9-3: SiI 0680A Internal Register Space – Base Address 1
9.3.1 IDE0 Task File Register 2
Address Offset: 00H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
IDE0 Task File Device Control
IDE0 Task File Auxiliary Status
Reserved
Reserved
This register defines one of the IDE Channel #0 Task File registers in the SiI 0680A. The register bits are also mapped to
Base Address 5, Offset 88H. See Section 9.7.27 for bit definitions.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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