SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
Address
Offset
Register Name
Access
Type
31
16
15
00
54H
58H
5CH
60H
64H
68H
6CH
70H
Reserved
Reserved
Reserved
-
-
-
Power Management Capabilities
Next Item Pointer
Capability ID
R/W
R/W
-
Data
Reserved
Functions Control and Status
Reserved
Reserved
-
Reserved
Reserved
PCI Bus Master
Status – IDE0
Reserved
PCI Bus Master
Command – IDE0
R/W
74H
78H
PRD Table Address – IDE0
PCI Bus Master Reserved
R/W
R/W
PCI Bus Master
Status – IDE1
Command – IDE1
7CH
80H
PRD Table Address – IDE1
Reserved
R/W
R/W
IDE0 Data
Transfer Mode
84H
Reserved
IDE1 Data
R/W
Transfer Mode
88H
8CH
90H
94H
System Configuration Status
System Software Data
System Command
R/W
R/W
R/W
R/W
FLASH Memory Address – Command + Status
Reserved
Flash Memory
Data
98H
EEPROM Memory Address – Command + Status
Reserved EEPROM Memory
R/W
R/W
9CH
Data
A0H
IDE0 TF Timing
IDE0
IDE1
Config IDE0
+ Status
Cmd
Cmd
R/W
+ Status
A4H
A8H
ACH
B0H
IDE0 Device 1 PIO Timing
IDE0 Device 1 DMA Timing
IDE0 Device 1 UDMA Timing
IDE1 TF Timing
IDE0 Device 0 PIO Timing
IDE0 Device 0 DMA Timing
IDE0 Device 0 UDMA Timing
Config IDE1
R/W
R/W
R/W
R/W
+ Status
+ Status
B4H
B8H
BCH
IDE1 Device 1 PIO Timing
IDE1 Device 1 DMA Timing
IDE1 Device 1 UDMA Timing
IDE1 Device 0 PIO Timing
IDE1 Device 0 DMA Timing
IDE1 Device 0 UDMA Timing
R/W
R/W
R/W
Table 9-1: SiI 0680A PCI Configuration Space (continued)
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
47
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