SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.1.1 Device ID – Vendor ID
Address Offset: 00H
Access Type: Read /Write
Reset Value: 0x0680_1095
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Device ID
Vendor ID
This register defines the Device ID and Vendor ID associated with the SiI 0680A. The register bits are defined below.
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Bit [31:16]: Device ID (R/W) – Device ID. This value in this bit field is determined by any one of three options:
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1) This field defaults to 0x0680 to identify the device as a Silicon Image SiI 0680A.
2) loaded from an external memory device : If an external memory device – FLASH or EEPROM – is
present with the correct signature, the PCI Class Code is loaded from that device after reset. The
correct signature for an EEPROM device is the data pattern 55AAH at addresses [03H:02H] and 55AAH
at addresses [01H:00H]. The correct signature for a FLASH device is the data pattern AA55H at
addresses [7FFFFH:7FFFEH] and 55H at address 7FFFCH. See chapter 8 for details.
3) system programmable : If Bit 0 of the Configuration register (40H) is set, to enables writes, the three
bytes are system programmable.
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Bit [15:00]: Vendor ID (R) – Vendor ID. This field defaults to 0x1095 to identify the vendor as Silicon
Image/CMD Technology.
9.1.2 PCI Status – PCI Command
Address Offset: 04H
Access Type: Read/Write/Write-One-to-Clear
Reset Value: 0x0290_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
This register defines the various control functions associated with the PCI bus. The register bits are defined below.
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Bit 31: Det. Par Err (R/W1C) – Detected Parity Error. This bit set indicates that the SiI 0680A detected a parity
error on the PCI bus-address or data parity error-while responding as a PCI target.
Bit 30: Sig. Sys Err (R/W1C) – Signaled System Error. This bit set indicates that the SiI 0680A signaled SERR
on the PCI bus.
Bit 29: Rcvd M Abort (R/W1C) – Received Master Abort. This bit set indicates that the SiI 0680A terminated a
PCI bus operation with a Master Abort.
Bit 28: Rcvd T Abort (R/W1C) – Received Target Abort. This bit set indicates that the SiI 0680A received a
Target Abort termination.
Bit 27: Sig. T Abort (R/W1C) – Signaled Target Abort. This bit set indicates that the SiI 0680A terminated a PCI
bus operation with a Target Abort.
Bit [26:25]: Devsel Timing (R) – Device Select Timing. This bit field indicates the DEVSEL timing supported by
the SiI 0680A. The hardwired value is 01B for Medium decode timing.
Bit 24: Det M Data Par Err (R/W1C) – Detected Master Data Parity Error. This bit set indicates that the SiI
0680A, as bus master, detected a parity error on the PCI bus. The parity error may be either reported by the
target device via PERR# on a write operation or by the SiI 0680A on a read operation.
Bit 23: Fast B-to-B Capable (R) – Fast Back-to-Back Capable. This bit is hardwired to 1 to indicate that the SiI
0680A is Fast Back-to-Back capable as a PCI target.
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Bit 22: Reserved (R).
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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SILICONIMAGE [ Silicon image ]
