SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
•
•
Bit 21: 66 MHz Capable (R) – 66 MHz PCI Operation Capable. This bit is hardwired to 0 to indicate that the SiI
0680A is not 66 MHz capable.
Bit 20: Capabilities List (R) – PCI Capabilities List. This bit is hardwired to 1 to indicate that the SiI 0680A has a
PCI Power Management Capabilities register linked at offset 34H.
•
•
Bit [19:10]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit 09: Fast B-to-B Enable (R) – Fast Back-to-Back Enable. This bit is hardwired to 0 to indicate that the SiI
0680A does not support Fast Back-to-Back operations as bus master.
•
Bit 08: SERR Enable (R/W) – SERR Output Enable. This bit set enables the SiI 0680A to drive the PCI SERR#
pin when it detects an address parity error. The Parity Error Response bit (06) must also be set to enable
SERR# reporting.
•
•
•
•
•
Bit 07: Address Stepping (R) – Address Stepping Enable. This bit is hardwired to 0 to indicate that the SiI
0680A does not support Address Stepping.
Bit 06: Par Error Response (R/W) – Parity Error Response Enable. This bit set enables the SiI 0680A to
respond to parity errors on the PCI bus. If this bit is cleared, the SiI 0680A will ignore PCI parity errors.
Bit 05: VGA Palette (R) – VGA Palette Snoop Enable. This bit is hardwired to 0 to indicate that the SiI 0680A
does not support VGA Palette Snooping.
Bit 04: Mem Wr & Inv (R) – Memory Write and Invalidate Enable. This bit is hardwired to 0 to indicate that the
SiI 0680A does not support Memory Write and Invalidate.
Bit 03: Special Cycles (R) – Special Cycles Enable. This bit is hardwired to 0 to indicate that the SiI 0680A does
not respond to Special Cycles.
•
•
Bit 02: Bus Master (R/W) – Bus Master Enable. This bit set enables the SiI 0680A to act as PCI bus master.
Bit 01: Memory Space (R/W) – Memory Space Enable. This bit set enables the SiI 0680A to respond to PCI
memory space access.
•
Bit 00: IO Space (R/W) – IO Space Enable. This bit set enables the SiI 0680A to respond to PCI IO space
access.
9.1.3 PCI Class Code – Revision ID
Address Offset: 08H
Access Type: Read/Write
Reset Value: 0x0101_8501
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PCI Class Code
PCI Prog Int
Revision ID
This register defines the various control functions associated with the PCI bus. The register bits are defined below.
•
Bit [31:08]: PCI Class Code (R) – PCI Class Code. This value in this bit field is determined by any one of three
options:
•
1) the default value, set by an external jumper:
If JP = 0, the value is 010400h for RAID mode
If JP = 1, the value is 010185h for ATA mode
•
2) loaded from an external memory device : If an external memory device – FLASH or EEPROM – is
present with the correct signature, the PCI Class Code is loaded from that device after reset. The
correct signature for an EEPROM device is the data pattern 55AAH at addresses [03H:02H] and 55AAH
at addresses [01H:00H]. The correct signature for a FLASH device is the data pattern AA55H at
addresses [7FFFFH:7FFFEH] and 55H at address 7FFFCH. See chapter 8 for details.
3) system programmable : If Bit 0 of the Configuration register (40H) is set, to enables writes, the three
bytes are system programmable.
•
•
Bit [07:00]: Revision ID (R) – Chip Revision ID. This bit field is hardwired to 01H to indicate the first revision
silicon.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
49
SILICONIMAGE [ Silicon image ]
