SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9. Register Definitions
This section describes the registers within the SiI 0680A PCI-ATA host controller ASIC.
9.1 PCI Configuration Space
The PCI Configuration Space registers define the operation of the SiI 0680A on the PCI bus. These registers are accessible
only when the SiI 0680A detects a Configuration Read or Write operation, with its IDSEL asserted, on the 32-bit PCI bus.
Table 9-1, outlines the PCI Configuration space for the SiI 0680A.
Address
Offset
Register Name
Access
Type
31
16
15
00
00H
04H
08H
0CH
10H
14H
18H
1CH
20H
24H
28H
2CH
30H
34H
38H
3CH
40H
44H
48H
4CH
50H
Device ID (0680h)
PCI Status
Vendor ID (1095h)
PCI Command
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
PCI Class Code
Header Type
Base Address Register 0
Revision ID
Cache Line Size
BIST
Latency Timer
Base Address Register 1
Base Address Register 2
Base Address Register 3
Base Address Register 4
Base Address Register 5
Reserved
Subsystem ID (0680h)
Expansion ROM Base Address
Reserved
Reserved
Interrupt Pin
Subsystem Vendor ID (1095h)
R/W
R/W
R
Capabilities Ptr
R/W
R/W
R/W
R/W
-
Max Latency
Min Grant
Reserved
Interrupt Line
Configuration
Software Data Register
Reserved
Reserved
-
Reserved
-
Table 9-1: PCI-680 PCI Configuration Space
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
46
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