SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
10. Design for Testability
The SiI 0680A chip features internal scan for testability and fault coverage at the ASIC level, and a NAND tree for testability of
the I/O pins at the board level. Test logic to support testing of the on-chip PLL is also included. Internal scan testing and PLL
testing requires several bypass modes in the ASIC clocking system. These operational and bypass modes are illustrated in
Fig. 10-1.
SYS_NAND_TEST
JP
Test
Register
1
0
Nand Tree
PCI_INTA_N
MEM_CS_N
Normal Function
Normal Function
0
1
4K
RST_PLL_TEST
PCI_IDSEL
BA5_EN
&
&
SCAN_MODE
&
1
0
PLL_TEST_CLK_SEL
P_CLK
33 MHz
2
2
3
&
SYS_IDE_CLKSEL[1:0]
PLL_TEST_MODE
3
2
TEST_MODE
PCI_GNT_N
&
0
1
133 MHz
1
I0_CLK
I1_CLK
0
( FB Clock )
(Ref Clock)
100 MHz
PLL
PCI_CLK
0
1
0
1
5ns
(Test Clock)
2
2
2
IDE0_DMARQ
PCI_CLK x 2
(Test Clock)
(Test Clock)
IDE0_CBLID_N
IDE1_CBLID_N
SCAN_EN
To all scan flip flops
Figure 10-1: SiI 0680A Clocking System and Test Feature Diagram
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
103
SILICONIMAGE [ Silicon image ]
