SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
10.4 PLL TEST
10.4.1 BYPASSING the VCO
The VCO in the analog phase-locked loop must be bypassed during digital logic simulation, to allow direct control of the PLL
output clock. When PLL_CPBIAS is forced high the reference clock (PCI_CLK) is muxed to the PLL output. Automatic test
equipment at the foundry also requires this test functionality to run the digital test vectors.
10.4.2 TESTING the VCO
A divide-by-4K counter is used to measure the VCO frequency for any controlled voltage at the PLL_LOOPFLT pin.
Normal Function
0
MEM_CS_N
1
4K
RST_PLL_TEST
PCI_IDSEL
&
&
SCAN_MODE
BA5_EN
&
1
PLL_TEST_CLK_SEL
P_CLK
33 MHz
0
2
2
3
&
PLL_TEST_MODE
TEST_MODE
PCI_GNT_N
&
( FB Clock )
(Ref Clock)
PLL
PCI_CLK
0
1
(Test Clock)
IDE0_DMARQ
PLL_CPBIAS
Figure 10-4: PLL Test Logic
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
107
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