SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
10.1 Test Mode Register
The test mode register selects the type of test to be performed and sets the I/O pins in the proper states. The test mode
register in the SiI 0680A is programmed through the JP and TEST_MODE input pins. The test mode register is cleared by PCI
reset. Table 10-1 lists the valid test mode settings. Register settings outside of those listed are ignored, and the chip operates
in normal mode.
1
0
1
0
0
0
0
1
JP
TEST_MODE
Figure 10-2: Test Mode Register Programming (A1H)
Test Mode Register
Description
Simulation test mode #0
A0H
A1H
AAH
Simulation test mode #1
NAND tree test mode
Table 10-1: Test Mode Register Selections
10.2 NAND Tree Test
The SiI 0680A features a NAND tree for parametric testing of the I/O pins. NAND tree testing allows the ASIC foundry to
validate input voltage thresholds and wire bond connections. At the board level, the NAND tree provides connectivity checks
between the PCB and package pins (signal pins only), in lieu of full JTAG boundary scan.
When the SiI 0680A is programmed for NAND tree test mode, all outputs and bi-directional pins are set to input mode. A logic
representation of the NAND tree is shown in Fig. 10-2. Refer to Table 10-2 for the NAND tree order.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
104
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