SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
21 IDE0_DA2
53 IDE1_CBLID_N
54 IDE1_DMACK_N
55 IDE1_INTRQ
56 IDE1_IORDY
57 IDE1_DMARQ
58 IDE1_RST_N
59 JP
85 PCI_SERR_N
86 PCI_PAR
22 IDE0_DIOR_N
23 IDE0_DIOW_N
24 IDE0_DMACK_N
25 IDE0_CBLID_N
26 IDE0_INTRQ
27 IDE0_IORDY
28 IDE0_DMARQ
29 IDE0_RST_N
30 IDE1_DD00
31 IDE1_DD01
32 IDE1_DD02
97 PCI_AD07
87 PCI_CBE1
88 PCI_AD15
89 PCI_AD14
90 PCI_AD13
91 PCI_AD12
92 PCI_AD11
93 PCI_AD10
94 PCI_AD09
95 PCI_AD08
96 PCI_CBE0
107 BA5_EN
108 PCI_CLK
109 SCAN_EN
110 MEM_CS_N
60 PCI_AD31
61 PCI_AD30
62 PCI_AD29
63 PCI_AD28
64 PCI_AD27
102 PCI_AD02
103 PCI_AD01
104 PCI_AD00
105 PCI_REQ_N
106 PCI_GNT_N
98 PCI_AD06
99 PCI_AD05
100 PCI_AD04
101 PCI_AD03
Table 10-2, SiI 0680A NAND Tree Order (continued)
10.3 Full Chip Internal Scan
The SiI 0680A generates SCAN_MODE internal signal by asserting logic “1” on the following input pins TEST_MODE,
BA5_EN, and PCI_GNT_N.
The SCAN_MODE signal selects the source for the scan clocks and sets internal latches open during scan. The internal
clocks for scan are provided as shown in Fig. 10-1, by the following pins:
External Input Pins:
PCI_CLK
Internal Scan Clock:
P_CLK
IDE0_CBLID
IDE1_CBLID
I0_CLK
I1_CLK
Additionally, SCAN_EN selects between normal inputs and scan inputs at all the scan flip-flops is provided by the input pin
SCAN_EN.
There are six scan chains with input pins and output pins as follows:
SCAN CHAIN
SCAN INPUT PIN
IDE0_DMARQ
IDE0_INTRQ
IDE0_IORDY
IDE1_DMARQ
IDE1_INTRQ
IDE1_IORDY
SCAN OUTPUT PIN
PCI_AD0
1
2
3
4
5
6
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
106
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