SiI0680A PCI to IDE/ATA
Data Sheet
Silicon Image, Inc.
9.7.52 Data Transfer Mode – IDE1
Address Offset: F4H
Access Type: Read/Write
Reset Value: 0x0000_0022
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
This register defines the transfer mode register for IDE Channel #1 in the SiI 0680A. The register bits are defined below.
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Bit [31:08]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [07:06]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [05:04]: Device 1 Transfer Mode (R/W) – IDE1 Device 1 Data Transfer Mode. This bit field is used to set the
data transfer mode on IDE side during PCI DMA transfer: 00B = PIO transfer with IORDY not monitored; 01B =
PIO transfer with IORDY monitored; 10B = normal DMA; and, 11B = Ultra DMA.
When this bit field is set to value other than 00B, SiI 0680A will monitor IORDY for normal PIO transfer.
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Bit [03:02]: Reserved (R). This bit field is reserved and returns zeros on a read.
Bit [01:00]: Device 0 Transfer Mode (R/W) – IDE0 Device 0 Data Transfer Mode. This bit field is used to set the
data transfer mode on IDE side during PCI DMA transfer: 00B = PIO transfer with IORDY not monitored; 01B =
PIO transfer with IORDY monitored; 10B = normal DMA; and, 11B = Ultra DMA.
When this bit field is set to value other than 00B, SiI 0680A will monitor IORDY for normal PIO transfer.
© 2006 Silicon Image, Inc.
SiI-DS-0069-C
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