C8051F52x-53x
Table 17.3. Manual Bit-Rate Parameters Examples
Baud
20 K
19.2 K
9.6 K
4.8 K
1 K
(bits/sec)
SYSCLK
(MHz)
25
24.5
24
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
312
306
300
276
200
306
300
276
200
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
325
319
312
288
208
319
312
288
208
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
325
319
312
288
208
319
312
288
208
3
3
3
3
3
3
3
3
3
1
1
1
1
1
0
0
0
0
325
319
312
288
208
319
312
288
208
19
19
19
19
19
19
19
19
19
1
1
1
1
1
0
0
0
0
312
306
300
276
200
306
300
276
200
22.1184
16
12.25
12
11.0592
8
17.4.4. Baud Rate Calculations - Automatic Mode
The designer may choose to use the automatic bit rate feature of the Slave Peripheral. In this case only the
prescaler and divider must be calculated as follows:
SYSCLK
4000000
1
ln2
---------------------
-------
prescaler = ln
×
– 1
SYSCLK
-----------------------------------------------------
2
divider =
(prescaler + 1) × 20000
In the following example it is calculated the value of these factors for a system clock (SYSCLK) of
24.5 MHz:
24500000
-----------------------
1
ln2
-------
prescaler = ln
×
– 1 = 1.615 ≅ 1
4000000
24500000
(1 + 1) × 20000
------------------------------------
2
divider =
= 306.25 ≅ 306
Table 17.4 presents some typical values of system clock and bit rate along with their factors.
164
Rev. 0.3
SILICON [ SILICON ]
