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C8051F530-IM 参数 Datasheet PDF下载

C8051F530-IM图片预览
型号: C8051F530-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 8/4/2 KB ISP功能的Flash MCU系列 [8/4/2 kB ISP Flash MCU Family]
分类和应用:
文件页数/大小: 220 页 / 2701 K
品牌: SILICON [ SILICON ]
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C8051F52x-53x  
This code fragment shows the procedure to schedule a message in a transmission operation:  
LINADDR = 0x08;  
// Select to transmit data  
LINDATA |= 0x20;  
LINADDR = 0x0E;  
// Point to ID  
LINDATA = 0x11;  
LINADDR = 0x0B;  
// Load the ID, in this example 0x11  
// Point to the size  
// Load the size with 8  
LINDATA = ( LINDATA & 0xF0 ) | 0x08;  
LINADDR = 0x00;  
// Point to Data buffer first byte  
for(i=0;i<8;i++)  
{
LINDATA = i + 0x41; // Load the buffer with 'A', 'B', 'C',……  
LINADDR++;  
}
LINADDR = LINCTRL;  
LINDATA = 0x01;  
// Start Transmission  
The following steps have to be performed by the application when an interrupt is requested.  
6. Check the DONE bit and the ERROR bit (LINST)  
7. Load the received data from the data buffer if the transfer was successful (for receive opera-  
tion only).  
8. If the transfer was not successful, check the error register to determine the kind of error. Fur-  
ther error handling has to be done by the application.  
9. Set the RSTINT and RSTERR bits in the status register (LINST) to reset the interrupt request  
and the error flags.  
17.4.6. LIN Slave Mode Operation  
Once initialized the LIN peripheral in Slave Mode can operate. Access from application to data buffer and  
ID registers of the LIN core slave is only possible when a data request is pending (DTREQ bit in LINST  
register is '1') and also when the LIN bus is not active (ACTIVE bit in LINST register set to '0').  
The LIN peripheral in slave mode detects the header of the message frame sent by the LIN master. If slave  
synchronization is enabled (autobaud), the slave synchronizes its internal bit time to the master bit time.  
An interrupt is requested in one of three situations:  
•After the reception of the IDENTIFIER FIELD  
•When an error is detected  
•When the message transfer is completed.  
The following steps have to be performed by the application when an interrupt is detected:  
•Check the DTREQ bit in the status register (LINST) is set. (Set when the IDENTIFIER FIELD has  
been received). If it is set then:  
•Read the identifier from the LINID register and process it  
•Adjust the TXRX bit in the control register (LINCTRL) (set to "1" if the current frame is a transmit oper-  
ation for the slave and set to "0" if the current frame is a receive operation for the slave)  
•Load the "data length" in the LINSIZE register (number of data bytes or value "1111b" if the data length  
should be decoded from the identifier)  
•Load the data to transmit into the data buffer. (for transmit operations only)  
•Set the DTACK bit in the LINCTRL register.  
166  
Rev. 0.3  
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