C8051F52x-53x
Table 12.1. Reset Electrical Characteristics
–40 to +125 °C unless otherwise specified.
Parameter
Conditions
= 8.5 mA, V = 2.1 V
Min
—
Typ
Max
Units
I
RST Output Low Voltage
—
0.8
V
OL
DD
0.7 x
RST Input High Voltage
—
—
—
V
V
V
DD
0.3 x
RST Input Low Voltage
RST Input Pullup Current
—
V
DD
RST = 0.0 V
—
14
1.7
2.2
TBD
TBD
TBD
µA
V
V
V
Monitor Threshold (V
Monitor Threshold (V
)
RST-LOW
TBD
TBD
DD
DD
)
V
RST-HIGH
Time from last system
clock rising edge to reset
initiation
Missing Clock Detector Timeout
Reset Time Delay
TBD
350
650
µs
Delay between release of
any reset source and
code execution at location
0x0000
TBD
TBD
—
—
—
—
µs
µs
Minimum RST Low Time to Generate a
System Reset
V
V
Monitor Turn-on Time
Monitor Supply Current
TBD
—
—
—
µs
DD
DD
V
= 2.1 V
23
TBD
µA
DD
Rev. 0.3
105
SILICON [ SILICON ]
