C8051F50x-F51x
Write to
0
PCA0CPLn
ENB
Reset
PCA0CPMn
Write to
PCA0CPHn
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
ENB
1
6 n n n
n
n
x
0 0
0
x
PCA Interrupt
PCA0CN
C C C C C C C C
F R C C C C C C
F F F F F F
PCA0CPLn
PCA0CPHn
5 4 3 2 1 0
0
1
Enable
Match
16-bit Comparator
TOGn
Toggle
0
CEXn
Crossbar
Port I/O
1
PCA
Timebase
PCA0L
PCA0H
Figure 27.6. PCA High-Speed Output Mode Diagram
27.3.4. Frequency Output Mode
Frequency Output Mode produces a programmable-frequency square wave on the module’s associated
CEXn pin. The capture/compare module high byte holds the number of PCA clocks to count before the out-
put is toggled. The frequency of the square wave is then defined by Equation 27.1.
FPCA
FCEXn = ------------------------------------------
2 PCA0CPHn
Note: A value of 0x00 in the PCA0CPHn register is equal to 256 for this equation.
Equation 27.1. Square Wave Frequency Output
Where FPCA is the frequency of the clock selected by the CPS[2:0] bits in the PCA mode register,
PCA0MD. The lower byte of the capture/compare module is compared to the PCA counter low byte; on a
match, CEXn is toggled and the offset held in the high byte is added to the matched value in PCA0CPLn.
Frequency Output Mode is enabled by setting the ECOMn, TOGn, and PWMn bits in the PCA0CPMn reg-
ister. Note that the MATn bit should normally be set to 0 in this mode. If the MATn bit is set to 1, the CCFn
flag for the channel will be set when the 16-bit PCA0 counter and the 16-bit capture/compare register for
the channel are equal.
Rev. 1.1
293
SILICON [ SILICON ]
