C8051F50x-F51x
Write to
0
PCA0CPLn
ENB
Reset
Write to
PCA0CPHn
ENB
PCA Interrupt
1
PCA0CPMn
P E C C M T P E
W C A A A O W C
M O P P T G M C
1 M P N n n n F
PCA0CN
C C C C C C C C
F R C C C C C C
F F F F F F
PCA0CPLn
PCA0CPHn
6 n n n
n
2 1 0 2 1 0
n
x
0 0
0 0
x
0
1
Enable
Match
16-bit Comparator
PCA
Timebase
PCA0L
PCA0H
Figure 27.5. PCA Software Timer Mode Diagram
27.3.3. High-Speed Output Mode
In High-Speed Output mode, a module’s associated CEXn pin is toggled each time a match occurs
between the PCA Counter and the module's 16-bit capture/compare register (PCA0CPHn and
PCA0CPLn). When a match occurs, the Capture/Compare Flag (CCFn) in PCA0CN is set to logic 1. An
interrupt request is generated if the CCFn interrupt for that module is enabled. The CCFn bit is not auto-
matically cleared by hardware when the CPU vectors to the interrupt service routine, and must be cleared
by software. Setting the TOGn, MATn, and ECOMn bits in the PCA0CPMn register enables the High-
Speed Output mode. If ECOMn is cleared, the associated pin will retain its state, and not toggle on the next
match event.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
292
Rev. 1.1
SILICON [ SILICON ]
