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C8051F502-IM 参数 Datasheet PDF下载

C8051F502-IM图片预览
型号: C8051F502-IM
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路PC时钟
文件页数/大小: 312 页 / 2813 K
品牌: SILICON [ SILICON ]
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C8051F50x-F51x  
27.2. PCA0 Interrupt Sources  
Figure 27.3 shows a diagram of the PCA interrupt tree. There are five independent event flags that can be  
used to generate a PCA0 interrupt. They are as follows: the main PCA counter overflow flag (CF), which is  
set upon a 16-bit overflow of the PCA0 counter, an intermediate overflow flag (COVF), which can be set on  
an overflow from the 8th, 9th, 10th, or 11th bit of the PCA0 counter, and the individual flags for each PCA  
channel (CCF0, CCF1, CCF2, CCF3, CCF4, and CCF5), which are set according to the operation mode of  
that module. These event flags are always set when the trigger condition occurs. Each of these flags can  
be individually selected to generate a PCA0 interrupt, using the corresponding interrupt enable flag (ECF  
for CF, ECOV for COVF, and ECCFn for each CCFn). PCA0 interrupts must be globally enabled before any  
individual interrupt sources are recognized by the processor. PCA0 interrupts are globally enabled by set-  
ting the EA bit and the EPCA0 bit to logic 1.  
(for n = 0 to 2)  
PCA0CPMn  
PCA0CN  
PCA0MD  
PCA0PWM  
P E C C M T P E  
W C A A A O W C  
M O P P T G M C  
1 M P N n n n F  
C C C C C C C C  
F R C C C C C C  
F F F F F F  
C WW C C C E  
I D D P P P C  
D T L S S S F  
L E C 2 1 0  
K
A C E  
C C  
L L  
S S  
E E  
L L  
1 0  
R O C  
S V O  
E F V  
L
5 4 3 2 1 0  
6 n n n  
n
n
PCA Counter/Timer 8, 9,  
10 or 11-bit Overflow  
Set 8, 9, 10, or 11 bit Operation  
0
1
PCA Counter/Timer 16-  
bit Overflow  
0
1
EPCA0  
EA  
ECCF0  
Interrupt  
Priority  
Decoder  
0
1
0
1
0
1
PCA Module 0  
(CCF0)  
ECCF1  
ECCF2  
0
1
PCA Module 1  
(CCF1)  
0
1
PCA Module 2  
(CCF2)  
ECCF3  
ECCF4  
ECCF5  
0
1
PCA Module 3  
(CCF3)  
0
1
PCA Module 4  
(CCF4)  
0
1
PCA Module 5  
(CCF5)  
Figure 27.3. PCA Interrupt Block Diagram  
27.3. Capture/Compare Modules  
Each module can be configured to operate independently in one of six operation modes: Edge-triggered  
Capture, Software Timer, High Speed Output, Frequency Output, 8 to 11-Bit Pulse Width Modulator, or 16-  
Bit Pulse Width Modulator. Each module has Special Function Registers (SFRs) associated with it in the  
CIP-51 system controller. These registers are used to exchange data with a module and configure the  
module's mode of operation. Table 27.2 summarizes the bit settings in the PCA0CPMn and PCA0PWM  
registers used to select the PCA capture/compare module’s operating mode. All modules set to use 8, 9,  
10, or 11-bit PWM mode must use the same cycle length (8-11 bits). Setting the ECCFn bit in a  
PCA0CPMn register enables the module's CCFn interrupt.  
Rev. 1.1  
289  
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