欢迎访问ic37.com |
会员登录 免费注册
发布采购

C8051F336 参数 Datasheet PDF下载

C8051F336图片预览
型号: C8051F336
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
 浏览型号C8051F336的Datasheet PDF文件第142页浏览型号C8051F336的Datasheet PDF文件第143页浏览型号C8051F336的Datasheet PDF文件第144页浏览型号C8051F336的Datasheet PDF文件第145页浏览型号C8051F336的Datasheet PDF文件第147页浏览型号C8051F336的Datasheet PDF文件第148页浏览型号C8051F336的Datasheet PDF文件第149页浏览型号C8051F336的Datasheet PDF文件第150页  
C8051F336/7/8/9  
1. The I2C-Bus and How to Use It (including specifications), Philips Semiconductor.  
2. The I2C-Bus Specification—Version 2.0, Philips Semiconductor.  
3. System Management Bus Specification—Version 1.1, SBS Implementers Forum.  
21.2. SMBus Configuration  
Figure 21.2 shows a typical SMBus configuration. The SMBus specification allows any recessive voltage  
between 3.0 V and 5.0 V; different devices on the bus may operate at different voltage levels. The bi-direc-  
tional SCL (serial clock) and SDA (serial data) lines must be connected to a positive power supply voltage  
through a pullup resistor or similar circuit. Every device connected to the bus must have an open-drain or  
open-collector output for both the SCL and SDA lines, so that both are pulled high (recessive state) when  
the bus is free. The maximum number of devices on the bus is limited only by the requirement that the rise  
and fall times on the bus not exceed 300 ns and 1000 ns, respectively.  
VDD = 5V  
VDD = 3V  
VDD = 5V  
VDD = 3V  
Master  
Device  
Slave  
Device 1  
Slave  
Device 2  
SDA  
SCL  
Figure 21.2. Typical SMBus Configuration  
21.3. SMBus Operation  
Two types of data transfers are possible: data transfers from a master transmitter to an addressed slave  
receiver (WRITE), and data transfers from an addressed slave transmitter to a master receiver (READ).  
The master device initiates both types of data transfers and provides the serial clock pulses on SCL. The  
SMBus interface may operate as a master or a slave, and multiple master devices on the same bus are  
supported. If two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme  
is employed with a single master always winning the arbitration. Note that it is not necessary to specify one  
device as the Master in a system; any device who transmits a START and a slave address becomes the  
master for the duration of that transfer.  
A typical SMBus transaction consists of a START condition followed by an address byte (Bits7–1: 7-bit  
slave address; Bit0: R/W direction bit), one or more bytes of data, and a STOP condition. Bytes that are  
received (by a master or slave) are acknowledged (ACK) with a low SDA during a high SCL (see  
Figure 21.3). If the receiving device does not ACK, the transmitting device will read a NACK (not acknowl-  
edge), which is a high SDA during a high SCL.  
The direction bit (R/W) occupies the least-significant bit position of the address byte. The direction bit is set  
to logic 1 to indicate a "READ" operation and cleared to logic 0 to indicate a "WRITE" operation.  
All transactions are initiated by a master, with one or more addressed slave devices as the target. The  
master generates the START condition and then transmits the slave address and direction bit. If the trans-  
146  
Rev. 0.2