欢迎访问ic37.com |
会员登录 免费注册
发布采购

C8051F336 参数 Datasheet PDF下载

C8051F336图片预览
型号: C8051F336
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
 浏览型号C8051F336的Datasheet PDF文件第144页浏览型号C8051F336的Datasheet PDF文件第145页浏览型号C8051F336的Datasheet PDF文件第146页浏览型号C8051F336的Datasheet PDF文件第147页浏览型号C8051F336的Datasheet PDF文件第149页浏览型号C8051F336的Datasheet PDF文件第150页浏览型号C8051F336的Datasheet PDF文件第151页浏览型号C8051F336的Datasheet PDF文件第152页  
C8051F336/7/8/9  
21.3.3. Clock Low Extension  
SMBus provides a clock synchronization mechanism, similar to I2C, which allows devices with different  
speed capabilities to coexist on the bus. A clock-low extension is used during a transfer in order to allow  
slower slave devices to communicate with faster masters. The slave may temporarily hold the SCL line  
LOW to extend the clock low period, effectively decreasing the serial clock frequency.  
21.3.4. SCL Low Timeout  
If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore,  
the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus  
protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than  
25 ms as a “timeout” condition. Devices that have detected the timeout condition must reset the communi-  
cation no later than 10 ms after detecting the timeout condition.  
When the SMBTOE bit in SMB0CF is set, Timer 3 is used to detect SCL low timeouts. Timer 3 is forced to  
reload when SCL is high, and allowed to count when SCL is low. With Timer 3 enabled and configured to  
overflow after 25 ms (and SMBTOE set), the Timer 3 interrupt service routine can be used to reset (disable  
and re-enable) the SMBus in the event of an SCL low timeout.  
21.3.5. SCL High (SMBus Free) Timeout  
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus  
is designated as free. When the SMBFTE bit in SMB0CF is set, the bus will be considered free if SCL and  
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the  
SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated  
following this timeout. Note that a clock source is required for free timeout detection, even in a slave-only  
implementation.  
21.4. Using the SMBus  
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting con-  
trol for serial transfers; higher level protocol is determined by user software. The SMBus interface provides  
the following application-independent features:  
Byte-wise serial data transfers  
Clock signal generation on SCL (Master Mode only) and SDA data synchronization  
Timeout/bus error recognition, as defined by the SMB0CF configuration register  
START/STOP timing, detection, and generation  
Bus arbitration  
Interrupt generation  
Status information  
Optional hardware recognition of slave address and automatic acknowledgement of address/data  
SMBus interrupts are generated for each data byte or slave address that is transferred. When hardware  
acknowledgement is disabled, the point at which the interrupt is generated depends on whether the hard-  
ware is acting as a data transmitter or receiver. When a transmitter (i.e. sending address/data, receiving an  
ACK), this interrupt is generated after the ACK cycle so that software may read the received ACK value;  
when receiving data (i.e. receiving address/data, sending an ACK), this interrupt is generated before the  
ACK cycle so that software may define the outgoing ACK value. If hardware acknowledgement is enabled,  
these interrupts are always generated after the ACK cycle. See Section 21.5 for more details on transmis-  
sion sequences.  
148  
Rev. 0.2