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C8051F336 参数 Datasheet PDF下载

C8051F336图片预览
型号: C8051F336
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
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C8051F336/7/8/9  
SFR Definition 20.16. P2MDIN: Port 2 Input Mode  
Bit  
7
6
5
4
3
2
1
0
Name  
Type  
Reset  
P2MDIN[7:0]  
R/W  
R
0
R
0
R
0
R
0
1
1
1
1
SFR Address = 0xF3  
Bit  
7:4  
3:0  
Name  
Function  
UNUSED  
Unused. Read = 0000b; Write = Don’t Care  
P2MDIN[3:0] Analog Configuration Bits for P2.3–P2.0 (respectively).  
Port pins configured for analog mode have their weak pullup, digital driver, and  
digital receiver disabled.  
0: Corresponding P2.n pin is configured for analog mode.  
1: Corresponding P2.n pin is not configured for analog mode.  
Note: Pins P2.1-P2.4 are only available in QFN24-packaged devices.  
SFR Definition 20.17. P2MDOUT: Port 2 Output Mode  
Bit  
7
6
5
4
3
2
1
0
Name  
Type  
Reset  
P2MDOUT[4:0]  
R/W  
R
0
R
0
R
0
0
0
0
0
0
SFR Address = 0xA6  
Bit  
Name  
Function  
Unused. Read = 000b; Write = Don’t Care  
7:5  
UNUSED  
4:0 P2MDOUT[4:0] Output Configuration Bits for P2.4–P2.0 (respectively).  
These bits are ignored if the corresponding bit in register P2MDIN is logic 0.  
0: Corresponding P2.n Output is open-drain.  
1: Corresponding P2.n Output is push-pull.  
Note: Pins P2.1-P2.4 are only available in QFN24-packaged devices.  
Rev. 0.2  
143