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C8051F336 参数 Datasheet PDF下载

C8051F336图片预览
型号: C8051F336
PDF下载: 下载PDF文件 查看货源
内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用: 微控制器和处理器外围集成电路
文件页数/大小: 234 页 / 3348 K
品牌: SILICON [ SILICON ]
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C8051F336/7/8/9  
Figure 21.4 shows the typical SCL generation described by Equation 21.2. Notice that T  
is typically  
HIGH  
twice as large as T  
. The actual SCL output may vary due to other devices on the bus (SCL may be  
LOW  
extended low by slower slave devices, or driven low by contending master devices). The bit rate when  
operating as a master will never exceed the limits defined by equation Equation 21.1.  
Timer Source  
Overflows  
SCL  
TLow  
THigh  
SCL High Timeout  
Figure 21.4. Typical SMBus SCL Generation  
Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA  
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.  
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable  
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times  
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 21.2 shows the min-  
imum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are typically  
necessary when SYSCLK is above 10 MHz.  
Table 21.2. Minimum SDA Setup and Hold Times  
EXTHOLD  
Minimum SDA Setup Time  
Minimum SDA Hold Time  
T
– 4 system clocks  
low  
or  
0
1
3 system clocks  
*
1 system clock + s/w delay  
11 system clocks  
12 system clocks  
*Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When  
using software acknowledgement, the s/w delay occurs between the time SMB0DAT  
or ACK is written and when SI is cleared. Note that if SI is cleared in the same write  
that defines the outgoing ACK value, s/w delay is zero.  
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low  
timeouts (see Section “21.3.4. SCL Low Timeout” on page 148). The SMBus interface will force Timer 3 to  
reload while SCL is high, and allow Timer 3 to count when SCL is low. The Timer 3 interrupt service routine  
should be used to reset SMBus communication by disabling and re-enabling the SMBus.  
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will  
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see  
Figure 21.4).  
150  
Rev. 0.2