C8051F39x/37x
SFR Definition 20.3. IPH: Interrupt Priority High
Bit
7
6
5
4
3
2
1
0
PHSPI0
PHT2
PHS0
PHT1
PHX1
PHT0
PHX0
Name
Type
Reset
R
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0x84; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7
6
Unused
PHSPI0
Read = 1, Write = Don't Care.
Serial Peripheral Interface (SPI0) Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the SPI0 interrupt.
5
4
3
2
PHT2
PHS0
PHT1
PHX1
Timer 2 Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the Timer 2 interrupt.
UART0 Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the UART0 interrupt.
Timer 1 Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the Timer 1 interrupt.
External Interrupt 1 Priority Control MSB.
This bit sets the MSB of the priority field for the External Interrupt 1 inter-
rupt.
1
0
PHT0
PHX0
Timer 0 Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the Timer 0 interrupt.
External Interrupt 0 Priority Control MSB.
This bit sets the MSB of the priority field for the External Interrupt 0 inter-
rupt.
120
Preliminary Rev. 0.71
SILICON [ SILICON ]
