C8051F39x/37x
SFR Definition 20.7. EIE2: Extended Interrupt Enable 2
Bit
7
6
5
4
3
2
1
0
EPTS
ET5
ET4
ESMB1
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xAF; SFR Page = All Pages
Bit
Name
Function
7:4
3
Reserved
EPTS
Must Write 0000b.
Enable Precision Temperature Sensor Interrupt.
This bit sets the masking of the Precision Temperature Sensor
interrupt.
0: Disable Precision Temperature Sensor interrupts.
1: Enable interrupt requests generated by the Precision Tempera-
ture Sensor.
2
1
0
ET5
ET4
Enable Timer 5 Interrupt.
This bit sets the masking of the Timer 5 interrupt.
0: Disable Timer 5 interrupts.
1: Enable interrupt requests generated by the TF5L or TF5H
flags.
Enable Timer 4 Interrupt.
This bit sets the masking of the Timer 4 interrupt.
0: Disable Timer 4 interrupts.
1: Enable interrupt requests generated by the TF4L or TF4H
flags.
ESMB1
Enable SMBus (SMB1) Interrupt.
This bit sets the masking of the SMB1 interrupt.
0: Disable all SMB1 interrupts.
1: Enable interrupt requests generated by SMB1.
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Preliminary Rev. 0.71
SILICON [ SILICON ]
