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C8051F390-A-GM 参数 Datasheet PDF下载

C8051F390-A-GM图片预览
型号: C8051F390-A-GM
PDF下载: 下载PDF文件 查看货源
内容描述: 50 MIPS 16 KB的闪存, 512B EEPROM混合信号MCU [50 MIPS 16 kB Flash, 512B EEPROM Mixed-Signal MCU]
分类和应用: 闪存可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 300 页 / 1709 K
品牌: SILICON [ SILICON ]
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C8051F39x/37x  
20.2. Interrupt Register Descriptions  
The SFRs used to enable the interrupt sources and set their priority level are described in this section.  
Refer to the data sheet section associated with a particular on-chip peripheral for information regarding  
valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s).  
SFR Definition 20.1. IE: Interrupt Enable  
Bit  
7
EA  
R/W  
0
6
ESPI0  
R/W  
0
5
4
3
2
1
0
Name  
Type  
Reset  
ET2  
R/W  
0
ES0  
R/W  
0
ET1  
R/W  
0
EX1  
R/W  
0
ET0  
R/W  
0
EX0  
R/W  
0
SFR Address = 0xA8; SFR Page = All Pages; Bit-Addressable  
Bit Name  
EA  
Function  
7
6
5
4
3
2
1
0
Enable All Interrupts.  
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.  
0: Disable all interrupt sources.  
1: Enable each interrupt according to its individual mask setting.  
ESPI0 Enable Serial Peripheral Interface (SPI0) Interrupt.  
This bit sets the masking of the SPI0 interrupts.  
0: Disable all SPI0 interrupts.  
1: Enable interrupt requests generated by SPI0.  
ET2  
ES0  
ET1  
EX1  
ET0  
EX0  
Enable Timer 2 Interrupt.  
This bit sets the masking of the Timer 2 interrupt.  
0: Disable Timer 2 interrupt.  
1: Enable interrupt requests generated by the TF2L or TF2H flags.  
Enable UART0 Interrupt.  
This bit sets the masking of the UART0 interrupt.  
0: Disable UART0 interrupt.  
1: Enable UART0 interrupt.  
Enable Timer 1 Interrupt.  
This bit sets the masking of the Timer 1 interrupt.  
0: Disable all Timer 1 interrupt.  
1: Enable interrupt requests generated by the TF1 flag.  
Enable External Interrupt 1.  
This bit sets the masking of External Interrupt 1.  
0: Disable external interrupt 1.  
1: Enable interrupt requests generated by the /INT1 input.  
Enable Timer 0 Interrupt.  
This bit sets the masking of the Timer 0 interrupt.  
0: Disable all Timer 0 interrupt.  
1: Enable interrupt requests generated by the TF0 flag.  
Enable External Interrupt 0.  
This bit sets the masking of External Interrupt 0.  
0: Disable external interrupt 0.  
1: Enable interrupt requests generated by the INT0 input.  
118  
Preliminary Rev. 0.71  
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