C8051F39x/37x
SFR Definition 20.6. EIP1H: Extended Interrupt Priority 1 High
Bit
7
6
5
4
3
2
1
0
PHT3
PHCP0
PHPCA0 PHADC0 PHWADC0 PHMAT
PHSMB0
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0x85; SFR Page = All Pages
Bit
Name
Function
7
PHT3
Timer 3 Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the Timer 3 interrupt.
Reserved. Must Write 0.
6
5
Reserved
PHCP0
Comparator0 (CP0) Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the CP0 interrupt.
4
3
2
1
0
PHPCA0
PHADC0
PHWADC0
PHMAT
Programmable Counter Array (PCA0) Interrupt Priority
Control MSB.
This bit sets the MSB of the priority field for the PCA0 interrupt.
ADC0 Conversion Complete Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the ADC0 Conversion
Complete interrupt.
ADC0 Window Comparator Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the ADC0 Window
interrupt.
Port Match Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the Port Match Event
interrupt.
PHSMB0
SMBus (SMB0) Interrupt Priority Control MSB.
This bit sets the MSB of the priority field for the SMB0 interrupt.
Preliminary Rev. 0.71
123
SILICON [ SILICON ]
