C8051F39x/37x
SFR Definition 20.2. IP: Interrupt Priority
Bit
7
6
5
4
3
2
1
0
PSPI0
PT2
PS0
PT1
PX1
PT0
PX0
Name
Type
Reset
R
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xB8; SFR Page = All Pages; Bit-Addressable
Bit
Name
Function
7
6
Unused
PSPI0
Read = 1, Write = Don't Care.
Serial Peripheral Interface (SPI0) Interrupt Priority Control
LSB.
This bit sets the LSB of the priority field for the SPI0 interrupt.
5
4
3
2
PT2
PS0
PT1
PX1
Timer 2 Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the Timer 2 interrupt.
UART0 Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the UART0 interrupt.
Timer 1 Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the Timer 1 interrupt.
External Interrupt 1 Priority Control LSB.
This bit sets the LSB of the priority field for the External Interrupt 1
interrupt.
1
0
PT0
PX0
Timer 0 Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the Timer 0 interrupt.
External Interrupt 0 Priority Control LSB.
This bit sets the LSB of the priority field for the External Interrupt 0
interrupt.
Preliminary Rev. 0.71
119
SILICON [ SILICON ]
