C8051F39x/37x
SFR Definition 20.5. EIP1: Extended Interrupt Priority 1
Bit
7
6
5
4
3
2
1
0
PT3
PCP0
PPCA0
PADC0
PWADC0
PMAT
PSMB0
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
SFR Address = 0xF6; SFR Page = All Pages
Bit
Name
Function
Timer 3 Interrupt Priority Control LSB.
7
PT3
This bit sets the LSB of the priority field for the Timer 3 interrupt.
Reserved. Must Write 0.
6
5
Reserved
PCP0
Comparator0 (CP0) Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the CP0 interrupt.
4
3
2
1
0
PPCA0
PADC0
PWADC0
PMAT
Programmable Counter Array (PCA0) Interrupt Priority
Control LSB.
This bit sets the LSB of the priority field for the PCA0 interrupt.
ADC0 Conversion Complete Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the ADC0 Conversion
Complete interrupt.
ADC0 Window Comparator Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the ADC0 Window
interrupt.
Port Match Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the Port Match Event
interrupt.
PSMB0
SMBus (SMB0) Interrupt Priority Control LSB.
This bit sets the LSB of the priority field for the SMB0 interrupt.
122
Preliminary Rev. 0.71
SILICON [ SILICON ]
