HDLC CONTROLLERS
S3C4510B
HDLC RX FIFO (HRXFIFO)
The Rx FIFO consists of eight 32-bit registers that are used for the buffer storage of the data received. Data
bytes are always transferred from a full register to an adjacent empty register. Each register has pointer bits that
indicate the frame status. When these pointers appear at the last 1-word or 4-word FIFO location, they update the
LAST bit(indicating the last of a frame), the OVERRUN bit, the CRC error bit, or Non-octet aligned bit.
The HRXFIFO data available (RxFA) status bits indicate the current state of the HRXFIFO. When the HRXFIFO
data status bit is '1', the HRXFIFO is ready to be read. The HRXFIFO data status is controlled by the 4-word or 1-
word transfer selection bit (Rx4WD). When an overrun occurs, the overrun frame of the HRXFIFO is no longer
valid.
An 'in frame' abort or a High level on nDCD input with the AutoEN bit in HCON is set to '1', the frame is cleared in
the HRXFIFO. (The last byte of the previous frame, which is separated by the frame boundary pointer, is
retained). Data in HRXFIFO should be read by word size.
The HRXFIFO is cleared by the Rx reset bit set to '1', an abort signal received, or nRESET.
RxFIFO
8-bit 8-bit
Data Valid
Last
OV
CRCE
NO
8-bit
8-bit
Rx Data
Figure 8-20. HDLC Rx FIFO Function Diagram
8-44
SAMSUNG [ SAMSUNG ]
