HDLC CONTROLLERS
S3C4510B
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
D D D D D D D D R D
R R R R R R R R R R
R
x
F
A
T
x
F
T T T
T
x
F
R
x
R
B
P P T T T R R R x
L L
T
x
x
x
x
x
x
x
I
x x x x
x
x x
x
x
x
x
x
x
I
M O N C A
F S D F
U S C
C T
T S
S
L L N N F N N F E A
T O O L D O L D R B
O V O R B D V D C D
A C
V
C T L
C D
D
M M
R T
E
E
[16] Rx abort (RxABT)
0= Normal operation
1 = Seven or more consecutive 1s have been received, in-frame condition.
[17] Rx CRC error (RxCRCE)
0 = Normal operation
1 = A frame Rx operation is completed with a CRC error.
[18] Rx non-octet align (RxNO)
0 = Received frame is octet.
1 = Received frame is not octet.
[19] Rx overrun (RxOV)
0 = Normal operation
1 = Received data is transferred into the RxFIFO when it is full.
[20] Rx memory overflow (RxMOV)
0 = Normal operation
1 = Indicates memory overflow when Rx buffer descriptor next pointer has null address.
[21] Reserved
[22] DMA Tx abort (DTxABT)
0 = Normal operation
1 = Abort signal is sended and DMA Tx enable bit is cleared.
[23] Rx internal error (RxIERR)
0 = Normal operation
1 = Received frame is not stable due to receive clock is unstable.
[24] DMA Rx frame done every received frame (DRxFD)
0 = Normal operation
1 = DMA Rx operation has successfully transferred a frame from RxFIFO to buffer memory.
[25] DMA Rx null list (DRxNL)
0 = Normal operation
1 = DMA Rx buffer descriptor pointer has a null address.
[26] DMA Rx not owner (DRxNO)
0 = DMA has the ownership.
1 = CPU has the ownership.
[27] DMA Tx frame done (DTxFD)
0 = Normal operation
1 = DMA Tx operation has successfully transferred a frame from memory to TxFIFO.
[28] DMA Tx null list (DTxNL)
0 = Normal operation
1 = DMA Tx buffer descriptor pointer has a null address.
[29] DMA Tx not owner (DTxNO)
0 = DMA has the ownership.
1 = CPU has the ownership.
[30] DPLL one clock missing (DPLLOM)
0 = Normal operation
1 = Set in FM/Machester mode when DPLL does not detect an edge on the first entry.
[31] DPLL two clock missing (DPLLTM)
0 = Normal operation
1 = DPLL was not detected on two consecutive edges and search mode was entered.
Figure 8-17. HDLC Status Register (Continued)
8-40
SAMSUNG [ SAMSUNG ]
