S3C4510B
HDLC CONTROLLERS
HDLC INTERRUPT ENABLE REGISTER (HINTEN)
Table 8-12. HINTENA and HINTENB Register
Registers
HINTENA
HINTENB
Offset
0x700c
0x800c
R/W
R/W
R/W
Description
Reset Value
0X00000000
0X00000000
HDLC Interrupt Enable Register
HDLC Interrupt Enable Register
Table 8-13. HINTEN Register Description
Description
Bit
Bit Name
Number
[3:0]
[4]
Reserved
TxFCIE
–
Tx frame complete interrupt enable
Tx FIFO available to write interrupt enable
–
[5]
TxFAIE
[6]
Reserved
TxSCTSIE
TxUIE
[7]
CTS transition has occurred interrupt enable
Tx under-run has occurred interrupt enable
Rx FIFO available to read interrupt enable
–
[8]
[9]
RxFAIE
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
[18]
[19]
[20]
[21]
[22]
[23]
[24]
[25]
[26]
[27]
[28]
[29]
[30]
[31]
Reserved
RxFDIE
Rx flag detected interrupt enable
–
Reserved
RxSDCDIE
RxFVIE
DCD transition interrupt enable
Rx frame valid interrupt enable
Idle detected interrupt enable
Abort detected interrupt enable
CRC error frame interrupt enable
Non-octet aligned frame interrupt enable
Rx overrun interrupt enable
Rx memory overflow interrupt enable
–
RxIDLEIE
RxABTIE
RxCRCEIE
RxNOIE
RxOVIE
RxMOVIE
Reserved
DTxABTIE
RxIERRIE
DRxFDIE
DRxNLIE
DRxNOIE
DTxFDIE
DTxNLIE
DTxNOIE
DPLLOMIE
DPLLTMIE
DMA Tx abort interrupt enable
Rx internal error interrupt enable
DMA Rx frame done interrupt enable
DMA Rx null list interrupt enable
DMA Rx not owner interrupt enable
DMA Tx frame done every transmitted frame interrupt enable
DMA Tx null list interrupt enable
DMA Tx not owner interrupt enable
DPLL one clock missing interrupt enable
DPLL two clocks missing interrupt enable
8-41
SAMSUNG [ SAMSUNG ]
