S3C4510B
HDLC CONTROLLERS
HDLC TX FIFO (HTXFIFO)
The Tx FIFO consists of eight 32-bit registers that are used for buffer storage of data to be transmitted. Data is
always transferred from a full register to an empty adjacent register. The Tx FIFO can be addressed at two
different register addresses: the 'frame continue' address and the 'frame terminate' address.
Each register has four pointers, data valid pointer bit (4 bits), last pointer bit, NoCRC pointer bit, Preamble
pointer bit. The data valid pointer bit indicates whether each byte is valid or not. The last byte pointer bit indicates
whether the frame to be sent has the frame last byte or not. The NoCRC pointer bit determines whether the CRC
data is to be appended or not by hardware.
When a valid data byte is written to the 'frame continue' address, the data valid pointer is set, but the last byte
pointer is not set. When a valid data byte is written to the 'frame terminate' address, the data valid pointer and
last byte pointer are set together. To reset these pointers, you write a '1' to either the TxABT bit or the TxRS bit in
the HCON register.
In DMA mode, when the DMA controller writes data to the HTxFIFO, Tx buffer descriptor Buffer Length field
value must be pre-set. However, if the Last bit is set in buffer descriptor, the last byte pointer in HTxFIFO is also
set. This means the last byte of the frame is in HTxFIFO. If the transmitted frame is longer than the Buffer
Length field value, the last byte pointer will not be set, and the next buffer descriptor having the last byte pointer
bit will be used.
The pointers continue shifting through the FIFO. When the transmitter detects a positive transition in the data
valid pointer at the last location of the FIFO, it initiates a frame with an opening flag. When it detects a negative
transition in the last byte pointer at the last location of the FIFO, it closes the frame, appending the CRC and a
closing flag follows.
The status of the Tx FIFO is indicated by the transmitter FIFO register available (TxFA) status bit. When TxFA =
'1', the Tx FIFO is available for loading data and data can be loaded into it. (This function is controlled by the
Tx4WD bit.) The HTxFIFO is reset by writing a '1' to the Tx reset, or the TxABT bit or by the nRESET. During a
reset operation, the TxFA status bit is suppressed and data loading is inhibited.
TxFIFO
8-bit 8-bit
Data Valid (4-bit)
Last (1-bit)
NoCRC
Preamble
8-bit
8-bit
8
Tx Data
Figure 8-19. HDLC Tx FIFO Function Diagram
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