HDLC CONTROLLERS
S3C4510B
Table 8-11. HSTAT Register Description (Continued)
Bit Name Description
Bit
Number
[23]
Rx internal error
(RxIERR)
This bit is set to '1' when received frame will be detected error possibility
due to the receive clock is unstable.
[24]
DMA Rx frame done
every received frame
(DRxFD)
This bit is set when a DMA Rx operation has successfully operated a frame
to memory from HRXFIFO, and when the last byte of a frame has been
written to memory. This bit generate interrupt when set to '1' to know a
frame is received. You can clear this bit by writing '1' to this bit.
[25]
[26]
[27]
[28]
[29]
DMA Rx null list
(DRxNL)
If this bit is set, the DMA Rx buffer descriptor pointer has a null address. In
this case, DMA Rx is disabled and the data transfer from the Rx FIFO to
buffer memory is discontinued. So the HRXFIFO is cleared. You can clear
this bit by writing '1' to this bit.
DMA Rx not owner
(DRxNO)
This bit is set, when DMA is not owner of the current buffer descriptor, and
DRxSTSK bit was set. In this case, DMA Rx is disabled and can generate
interrupt, if enabled. If DRxSTSK bit is zero, this bit is always zero. You
can clear this bit by writing '1' to this bit.
DMA Tx frame done
(DTxFD)
In case of MFF bit is '0' (default), when DNA Tx operation has successfully
transferred rest byte of frame from Tx FIFO to destination, this bit will be
set to ’1’. But if MFF is set to ’1’, transceiver will keep sending the data
until there is no data transfer from memory to TxFIFO.
DMA Tx null list
(DTxNL)
If this bit is set '1', the DMA Tx buffer descriptor pointer has a null address.
In this case, DMA Tx is disabled and the data to be transferred
discontinued from the buffer memory to Tx FIFO. You can clear this bit by
writing '1' to this bit.
DMA Tx not owner
(DTxNO)
This bit is set, when DMA is not owner of the current buffer descriptor, and
DTxSTSK bit was set. In this case, DMA Tx disabled and can generate
interrupt, if enabled. If DTxSTSK bit is zero, this bit is always zero. You
can clear this bit by writing '1' to this bit.
[30]
[31]
DPLL one clock missing When operating in FM/Manchester mode, the DPLL sets this bit to '1' if it
(DPLLOM)
does not detect an edge in its first attempt. You can clear this bit by writing
a '1' to this bit.
DPLL two clock missing When it is operating in the FM/Manchester mode, the DPLL sets this bit to
(DPLLTM)
'1' if it does not detect an edge in two successive attempts. At the same
time the DPLL enters Search mode. In NRZ/NRZI mode, and while the
DPLL is disabled, this bit is always '0'. You can clear this bit by writing a '1'
to this bit.
8-38
SAMSUNG [ SAMSUNG ]
