S3C4510B
HDLC CONTROLLERS
HDLC STATUS REGISTER (HSTAT)
NOTE
Reading the HDLC status register is a non-destructive process. The method used to clear a High-level
status condition depends on the bit's function and operation mode (DMA or interrupt). For details, please
see the description of each status register.
Table 8-10. HSTATA and HSTATB Register
Registers
HSTATA
HSTATB
Offset
0x7008
0x8008
R/W
R/W
R/W
Description
Reset Value
0X00000000
0X00000000
HDLC Channel A Status Register
HDLC Channel B Status Register
SUMMARY
There are two kinds of bits in a status register.
1. TxFA, TxCTS, RxFA, RxDCD, RxFV, RxCRCE, RxNO, RxIERR, and RxOV bits are show each bit's
status. These bits are set or cleared automatically according to the each bit status.
2. All other bits are cleared by the CPU writing '1' to each bit.
8-35