HDLC CONTROLLERS
S3C4510B
HDLC SPECIAL REGISTERS
The HDLC special registers are defined as read-only or write-only registers according to the direction of
information flow. The addresses of these registers are shown in Table 8-4 and 8-5.
The transmitter FIFO register can be accessed using two different addresses, the frame terminate address and
the frame continue address. The functions of these addresses are discussed in detail in the FIFO section below.
Table 8-4. HDLC Channel A Special Registers
Registers
HMODE
Offset
0´ 7000
R/W
R/W
R/W
R/W
R/W
W
Description
HDLC mode register
Reset Value
0´ 00000000
0´ 00000000
0´ 00000000
0´ 00000000
–
HCON
HDLC control register
0´ 7004
0´ 7008
0´ 700c
0´ 7010
HSTAT
HINTEN
HDLC status register
HDLC interrupt enable register
HTxFIFO frame continue register
HTxFIFOC
(Frame Continue)
HTxFIFOT
(Frame
W
HTxFIFO frame terminate register
–
0´ 7014
Terminate)
HRxFIFO
HBRGTC
HPRMB
R
HRxFIFO entry register
0´ 7018
0´ 701c
0´ 7020
0´ 7024
0´ 7028
0´ 702c
0´ 7030
0´ 7034
0´ 7038
0´ 703c
0´ 7040
0´ 7044
0´ 00000000
0´ 00000000
0´ 00000000
0´ 00000000
0´ 00000000
0´ 00000000
0´ 00000000
0´ 00000000
0´ FFFFFFFF
0´ FFFFFFFF
0´ XXXX0000
0´ XXXX0000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
HDLC BRG time constant register
HDLC preamble register
HSAR0
HDLC station address 0
HSAR1
HDLC station address 1
HSAR2
HDLC station address 2
HSAR3
HDLC station address 3
HMASK
HDLC mask register
HDMATxPTR
HDMARxPTR
HMFLR
DMA Tx buffer descriptor pointer
DMA Rx buffer descriptor pointer
Maximum frame length register
Receive buffer size register
HRBSR
8-24
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