HDLC CONTROLLERS
S3C4510B
RECEIVE BUFFER DESCRIPTOR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
O
Buffer Data Pointer
Reserved
F
L
V
A D
L F B T
T M
Reserved
O N C
V O D
Buffer Length
Next Buffer Descriptor Pointer
[30:0] Buffer Data Pointer
[31] Ownership (O)
0 = CPU
1 = DMA
[15:0] Buffer Length
Received buffer lengths are wrote to this buffer descriptor
Rx Status Bits
This bits may be regarded as valid when L bit (in Rx status bit) is set.
[16] CD Lost (CD)
0 = Normal
1 = CD lost occurs
[17] CRC Error (CE)
0 = Normal
1 = CRC error occurs to the frame received.
[18] Non-octet Aligned Frame (NO)
0 = Normal
1 = Non-octet aligned frame is reveived.
[19] Over-run (OV)
0 = Normal
1 = The reveived frame overruns.
[20] DPLL Two Miss (DTM)
0 = Normal
1 = DPLL two miss clock occurs.
[21] Rx Abort (ABT)
0 = Normal
1 = The received frame aborted.
[22] First In Frame (F)
0 = This buffer descriptor status is not the first to the frame.
1 = This buffer descriptor status is the first to the frame.
[23] Last In Frame (L)
0 = This buffer descriptor status is not the last to the frame.
1 = This buffer descriptor status is the first to the frame.
[24] Frame Length Violation (FLV)
0 = Normal
1 = This received frame length exceeds the value of the maximum frame length register.
[31:0] Next Buffer Descriptor Pointer
The address of the next buffer descriptor
Figure 8-11. Receive Buffer Descriptor
8-22
SAMSUNG [ SAMSUNG ]
