HDLC CONTROLLERS
S3C4510B
HDLC GLOBAL MODE REGISTER
Table 8-6. HMODEA and HMODEB Register
Registers
HMODEA
HMODEB
Offset
0´ 7000
0´ 8000
R/W
R/W
R/W
Description
HDLC Mode register
HDLC Mode register
Reset Value
0´ 00000000
0´ 00000000
Table 8-7. HMODE Register Description
Description
Bit
Bit Name
Number
[0]
Multi-Frame in HTxFIFO If this bit is set, more than one frame can be loaded into HTxFIFO. In this
in DMA operation (MFF) case, the frame size may be less than the FIFO size.
[1]
[2]
Reserved
Not applicable.
Rx clock
inversion(RXCINV)
If this bit set to '0', the receive clock samples the data at the rising edge.
If this bit set to '1', the receive clock samples the data at the falling edge.
[3]
[4]
Tx clock
inversion(TXCINV)
If this bit set to '0', the transmit clock shifts the data at the falling edge.
If this bit set to '1', the transmit clock shifts the data at the rising edge.
Rx Little-Endian mode
(RxLittle)
This bit determines whether the data is in Little- or Big-endian format.
HRXFIFO is in Little-endian. If this bit is set to '0', then the data on the
system bus should be in Big-endian. Therefore the bytes will be swapped
in Big- endian.
[5]
Tx Little-Endian mode
(TxLittle)
This bit determines whether Tx data is in Little or Big endian (TxLittle)
format. HTxFIFO is in Little-endian. If this bit is set to '1', the data on the
system bus is Little endian. If this bit is set to '0', the data on the system
bus is in Big-endian. (that is, the data bytes are swapped to be Little
endian format.)
[7:6]
Reserved
Not applicable
[10:8] Tx preamble
length(TxPL)
These bits determine the length of preamble to be sent before the opening
flag when the TxPRMB bit is set in the control register.
000 1byte, 001 2bytes,and 111 8bytes will be sent.
Not applicable
[11]
Reserved
[14:12] Data formats (DF)
When the DF bits are '000', data is transmitted and received in the NRZ
data format. When DF is '001', the NRZI (zero complement) data format is
selected. DF = '010' selects the FM0 data format, DF = '011' the FM1 data
format, and DF = '100' the Manchester data format.
[15]
Reserved
Not applicable
[18:16] DPLL clock select
(DPLLCLK)
Using this setting, you can configure the clock source for DPLL to one of
the following pins: TxC, RxC, MCLK, BRGOUT1, or BRGOUT2. To select
one of these pins, set the DPLLCLK bits to '000', '001', '010', '011', or '100',
respectively.
8-26
SAMSUNG [ SAMSUNG ]
