HDLC CONTROLLERS
S3C4510B
DATA BUFFER DESCRIPTOR
The ownership bit in the MSB of the buffer data pointer controls the ownership of the descriptor. When the
ownership bit is '1', the DMA controller owns the descriptor. When this bit is '0', the CPU has the descriptor. The
owner of the descriptor always owns the associated data frame. (The descriptor's buffer data pointer field always
points to this buffer for about a frame.)
As it receives the data, the software sets the maximum frame length register. If the received data is longer than
the value of the maximum frame length register, this frame is ignored and the FLV bit is set. The software also
sets the DMA Rx buffer descriptor pointer to point to a chain of buffer descriptors, all of which have their
ownership bit.
The DMA controller can be started to set the DMA Rx enable bit in the control register. When a frame is
received, it is moved into memory at the address specified by the DMA Rx data buffer pointer. If a frame is
longer than the value of the RxBuf Size register, then the next buffer descriptors are fetched to receive the
frame.
That is, to handle a frame, one or more buffer descriptors could be used. Please note that no configurable offset
or page boundary calculation is required. The received frame is moved to the buffer memory whose address is
pointed to by the buffer data pointer until the end of frame, or until the length exceeds the maximum frame length
configured.If the length exceeds the maximum frame length configured, the frame length violated bit is set.
If the entire frame is received successfully, the status bits in the receive buffer descriptor are set to indicate the
received frame status. The ownership bit in the buffer descriptor pointer is cleared by the CPU which has the
ownership and an interrupt may now be generated. The DMA controller copies the next buffer descriptor pointer
into the DMA Rx buffer descriptor pointer register.
If the next buffer descriptor pointer is null(0), the DRxEN bit is cleared, and DMA Rx operation is stopped.
Otherwise, the descriptor is read, and the DMA controller starts again with the next data, as described in the
previous paragraph.
When the DMA reads a descriptor, if the ownership bit is not set, it has two options:
— Skip to the next buffer descriptor when DRxSTSK bit is '0'
— Generate an interrupt and halt the DMA operation when DRxSTSK bit is '1'
During transmission, the two-byte frame length at the Tx buffer descriptor is moved to the DMA internal Tx
register. After transmission, the Tx status is saved in the Tx buffer descriptor. The DMA controller then updates
the next buffer descriptor pointer for the linked list structure.
When the DMA Tx buffer descriptor register points to the first buffer descriptor, the transmitter starts transmitting
the frame data from the buffer memory to Tx FIFO.
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