S3C4510B
HDLC CONTROLLERS
BUFFER DESCRIPTOR
TRANSMIT BUFFER DESCRIPTOR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8 7 6 5 4 3 2 1 0
O
Buffer Data Pointer
Reserved
WA D L E N P
Reserved
T
Buffer Length
Next Buffer Descriptor Pointer
[30:0] Buffer Data Pointer
[31] Ownership (O)
0 = CPU
1 = DMA
Tx Control Bits
[0] Preamable (P)
0 = No preamble
1 = Preamble
[1] TxNoCRC Mode (N)
0 = CRC mode
1 = No CRC mode
1 = Little-endian
[2] Little-Endian Mode (E)
0 = Big-endian
[3] Last (L)
0 = This is not the last buffer in the frame.
1 = This is the last buffer in the frame.
[4] Buffer Data Pointer Decrement (D)
0 = Increment
1 = Decrement
[6:5] Widget Aligment Control (WA)
00 = No invalid bytes
10 = 2 invalid bytes
01 = 1 invalid bytes
11 = 3 invalid bytes
[23:0] Buffer Length
Tx Status Bit
These bit may be regarded as valid when the L bit (in Tx control bit) is set.
[26] Transmission Completion (T)
0 = Normal
1 = One frame completed
[31:0] Next Buffer Descriptor Pointer
The address of the next buffer descriptor
Figure 8-10. Transmit Buffer Descriptor
8-21
SAMSUNG [ SAMSUNG ]
