S3C4510B
HDLC CONTROLLERS
Table 8-5. HDLC Channel B Special Registers
Registers
Offset
0´ 8000
R/W
R/W
R/W
R/W
R/W
W
Description
HDLC mode register
Reset Value
0´ 00000000
0´ 00000000
0´ 00000000
0´ 00000000
–
HMODE
HCON
HDLC control register
0´ 8004
0´ 8008
0´ 800c
0´ 8010
HSTAT
HINTEN
HDLC status register
HDLC interrupt enable register
HTxFIFO frame continue register
HTxFIFOC
(Frame Continue)
HTxFIFOT
(Frame
W
HTxFIFO frame terminate register
–
0´ 8014
Terminate)
HRxFIFO
HBRGTC
HPRMB
R
HRxFIFO entry register
0´ 8018
0´ 801c
0´ 8020
0´ 8024
0´ 8028
0´ 802c
0´ 8030
0´ 8034
0´ 8038
0´ 803c
0´ 8040
0´ 8044
0´ 00000000
0´ 00000000
0´ 00000000
0´ 00000000
0´ 00000000
0´ 00000000
0´ 00000000
0´ 00000000
0´ FFFFFFFF
0´ FFFFFFFF
0´ XXXX0000
0´ XXXX0000
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
HDLC BRG time constant register
HDLC preamble register
HSAR0
HDLC station address 0
HSAR1
HDLC station address 1
HSAR2
HDLC station address 2
HSAR3
HDLC station address 3
HMASK
HDLC mask register
HDMATxPTR
HDMARxPTR
HMFLR
DMA Tx buffer descriptor pointer
DMA Rx buffer descriptor pointer
Maximum frame length register
Receive buffer size register
HRBSR
8-25
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