S3C4510B
HDLC CONTROLLERS
Receiver DMA Mode
To use DMA operation without CPU intervention, you have to make Rx buffer descriptor chain in advance. And
set the DMA Rx buffer descriptor pointer (DMARxPTR) register to the address of the first buffer descriptor of the
chain, and then DMA Rx channel should be enabled.
HARDWARE FLOW CONTROL
TxClock
TxD
last
RTS
CTS
Figure 8-7. nCTS Already Asserted
When nCTS is active and there exists data to be transmitted in Tx FIFO, nRTS enters Low, allowing data
transmission. At the beginning of the data is an open flag while at the end a closing flag. If the frame being
transferred discontinues, nRTS goes back to the High after the data transmission is completed.
TxClock
TxD
RTS
CTS
Data
5-13 cycles
14 - 22 cycles
Figure 8-8. CTS Lost during Transmission
When the condition of nCTS is shifted from Low to High, it is detected at the falling edge of Tx clock, where
nRTS also goes High. For about 5 to 13 cycles after nRTS enters High, the data transmission continues. nRTS
remains High for a maximum of 22 cycles and goes back to the Low condition if there remains any data to be
transmitted in HTxFIFO. If nCTS is still High even when nRTS went back to Low, not the data in HTxFIFO but a
mark idle pattern is transmitted when AutoEn bit set to one.
8-17
SAMSUNG [ SAMSUNG ]
