S3C4510B
HDLC CONTROLLERS
Transmitter Interrupt Mode
The first byte of a frame (the address field) should be written into the Tx FIFO at the 'frame continue' address.
Then, the transmission of the frame data starts automatically. The bytes of the frame continue to be written into
the Tx FIFO as long as data is written to the 'frame continue' address. The HDLC logic keeps track of the field
sequence within the frame.
The frame is terminated when the last frame data is written to the Tx FIFO's 'frame terminate' address. The FCS
field is automatically appended by hardware, along with a closing flag. Data for a new frame can be loaded into
the Tx FIFO immediately after the previous frame data, if TxFA is '1'. The closing flag can serve as the opening
flag of the next frame or separate opening and closing flags can be transmitted. If a new frame is not ready to be
transmitted, a flag time fill or mark idle pattern is transmitted automatically.
If the Tx FIFO becomes empty at any time during the frame transmission, an underrun occurs and the transmitter
automatically terminates the frame by transmitting an abort. The underrun state is indicated when the transmitter
underrun status bit (TxU) is '1'.
Whenever you set the transmission abort control bit (TxABT in HCON), the transmitter immediately aborts the
frame (transmits at least eight consecutive 1s), clearing the Tx FIFO. If the transmission abort extension control
bit (TxABTEXT) is set at the time, an idle pattern (at least 16 consecutive 1s) is transmitted. An abort or idle in an
out- of-frame condition can be useful to gain 8 or 16 bits of delay time between read and write operations.
Transmitter DMA Mode
To use DMA operation without CPU intervention, you have to make Tx buffer descriptor chain in advance. And
set the DMA Tx buffer descriptor pointer (DMATxPTR) register to the address of the first buffer descriptor of the
chain, and then DMA Tx channel should be enabled.
When Tx underrun or CTS lost condition occurs during DMA operation, DMA Tx enable bit(HCON[6]) is cleared
and DMA Tx operation is stopped. This situation is reported to system with DTxABT bit set (HSTAT[22]).
In case of Tx underrun, abort signal sent and then idle pattern is sent if TxEN bit is set. In case of CTS lost, TxD
output goes high state as long as CTS remains high level.
8-15
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