HDLC CONTROLLERS
S3C4510B
HDLC RECEIVER OPERATION
The HDLC receiver is provided with data and a pre-synchronized clock by means of the RxD and the internal
DPLL clock, the TxC pin, or the RxC pin. The data is a continuous stream of binary bits. One of the
characteristics of this bit stream is that a maximum of five consecutive 1s can occur unless an abort, flag, or idle
condition occurs. The receiver continuously searches (bit-by-bit) for flags and aborts.
When a flag is detected, the receiver synchronizes the frame to the flag timing. If a series of flags is received,
the receiver re-synchronizes the frame to each successive flag.
If the frame is terminated because of a short frame condition (frame data is less than 32 bits after an opening
flag), the frame is simply ignored. Noise on the data input line (RxD) during time fill can cause this kind of invalid
frame.
The received data which is clocked by the external TxC or RxC, or by an internal DPLL or BRG source enters a
56-bit or 32-bit shift register before it is transferred into the HRXFIFO. Synchronization is established when a flag
is detected in the first eight locations of the shift register. When synchronization has been achieved, data is
clocked through to the last byte location of the shift register where it is transferred into the HRxFIFO.
In 1-word transfer mode, when the HRxFIFO available bit (RxFA) is '1', data is available at least in one-word. In
4-word transfer mode, the RxFA is '1' when data is available in the last four FIFO register locations (registers 4,
5, 6, and 7). The nDCD input is provided for a modem or other hardware interface. If AutoEN bit in HCON[28] is
set to '1', the receiver operation is dependent on the nDCD input level.
Otherwise, receiver operation is free of the nDCD input level.
Receiver Interrupt Mode
Whenever data is available in the HRXFIFO, an interrupt is generated by RxFA (if the interrupt is enabled). The
CPU reads the HDLC status register either in response to the interrupt request or in turn during a polling
sequence.
When the received data available bit(RxFA) is '1', the CPU can read the data from the HRXFIFO. If the CPU
reads normal data or address data from the HRXFIFO, the RxFA bit is automatically cleared.
In CRC mode, the 16 bits preceding the closing flag are regarded as the FCS and checked by hardware, and they
are transferred to the HRXFIFO. Also, in no CRC mode, without the hardware checking, all data bits preceding
the closing flag are transferred to the HRXFIFO. When the closing flag is sent to the receiver, the frame is
terminated. Whatever data is present in the most significant byte of the receiver, the shift register is right justified
and transferred to the HRXFIFO. The frame boundary pointer, which is explained in the HRXFIFO register
section, is set simultaneously in the HRXFIFO. When the last byte of the frame appears at the 1-word or 4-word
boundary location of the HRXFIFO, depending on the settings of the Rx4WD control bit, the frame boundary
pointer sets the frame valid status bit (if the frame is completed with no error) or the RxCRCE status bit(if the
frame was completed, but with a CRC error).
If the frame reception is completed, an RxCRCE interrupt (for a frame error) or an RxFV interrupt (for normal
state) is generated. At this point, the CPU can read the Rx remaining bytes (RxRB) status bits to know how many
bytes of this frame still remain in the HRXFIFO.
When you set the frame discontinue control bit (the incoming frame discard control bit) to '1', the receiver
discards the current frame data without dropping the flag synchronization. You can use this feature to ignore a
frame with a non-matched address.
8-16
SAMSUNG [ SAMSUNG ]
