S3C4510B
ETHERNET CONTROLLER
Content Address Memory (CAM) Register
There are 21 CAM entries for the destination address and the pause control packet. For the destination address
CAM value, one destination address consists of 6 bytes. Using the 32-word space (32 ´ 4 bytes), you can
therefore maintain up to 21 separate destination addresses.
You use CAM entries 0, 1, and 18 to send pause control packets. To send a pause control packet, you write the
CAM0 entry with the destination address, the CAM1 entry with the source address, and the CAM 18 entry with
length/type, opcode, and operand. You then set the send pause bit in the MAC transmit control register.
Table 7-15. CAM Register
Registers
CAM
Offset
R/W
Description
Reset Value
0x9100–0x917C
W
CAM content (32 words)
Undefined
Table 7-16. Content Address Memory (CAM) Register Description
Bit Number
Bit Name
Description
[31:0]
CAM content (CAM)
The CPU uses the CAM content register as a data base for
destination address. To activate the CAM function, you must
set the appropriate enable bits in CAM enable register.
7-33
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