S3C4510B
ETHERNET CONTROLLER
MAC Control Register
The MAC control register provides global control and status information for the MAC. The missed roll/link10 bit is
a status bit. All other bits are MAC control bits.
MAC control register settings affect both transmission and reception. You can also control transmit and receive
operations separately. To select customized operating features, you should write this register during power-up.
This way, you will not need to write or read it again during normal operation.
After a reset is complete, the MAC controller clears the reset bit. Not all PHYs support full-duplex operation.
(setting the MAC loopback bit overrides the full-duplex bit.) Also, some 10-Mb/s PHYs may interpret the loop10
bit to control different functions, and manipulate the link10 bit to indicate a different status condition.
Table 7-18. MACON Register
Registers
MACON
Offset
R/W
Description
Reset Value
0XA000
R/W
MAC control
0x00000000
Table 7-19. MAC Control Register Description
Bit Name Description
Bit Number
[0]
Halt request (HaltReq)
Set this bit to stop data packet transmission and reception as
soon as Tx/Rx of any current packets has been completed.
[1]
[2]
Halt immediate (HaltImm)
Software reset (Reset)
Set this bit to immediately stop all transmission and reception.
Set this bit to reset all MAC control and status register and
MAC state machines.
[3]
[4]
Full-duplex (FullDup)
Set this bit to start transmission while reception is in progress.
MAC loopback (MACLoop)
Set this bit to cause transmission signals to be presented as
input to the receive circuit without leaving the controller.
[5]
[6]
Reserved
MII-OFF
Not applicable
Use this bit to select the connection mode. If this bit is set to
one, 10 M bits/s interface will select the 10 M bits/s endec.
Otherwise, the MII will be selected.
[7]
Loop 10 Mb/s (Loop10)
If this bit is set, the Loop_10 external signal is asserted to the
10-Mb/s endec.
[9:8]
[10]
Reserved
Not applicable.
Missed roll (MissRoll)
This bit is automatically set when the missed error counter
rolls over.
[11]
[12]
Reserved
MDC-OFF
Not applicable.
Clear this bit to enable the MDC clock generation for power
management. If it is set to one, the MDC clock generation is
disabled.
[13]
Enable missed roll
(EnMissRoll)
Set this bit to generate an interrupt whenever the missed error
counter rolls over.
[14]
[15]
Reserved
Not applicable
Link status 10 Mb/s (Link10)
Reserved
This bit value is read as a buffered signal on the link 10 pin.
Not applicable.
[31:16]
7-35
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